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Authors:
Linda Null ,julia Lobur
Chapter:
A Closer Look At Instruction Set Architectures
Exercise:
Exercises
Question:20 | ISBN:9780763704445 | Edition: 3

Question

20. Suppose an instruction takes four cycles to execute in a non-pipelined CPU: one cycle to fetch the instruction, one cycle to decode the instruction, one cycle to perform the ALU operation, and one cycle to store the result. In a CPU with a 4-stage pipeline, that instruction still takes four cycles to execute, so how can we say the pipeline speeds up the execution of the program?

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