Associative cache :

1. Needs comparison with all tag bits, i.e., the cache control logic must examine every block’s tag for a match at the same time in order to determine that a block is in the cache/not.
2. Main Memory Address is divided into 1 fields : TAG & WORD.
3. The mapping of the main memory block can be done with any of the cache block.
4. If the processor need to access same memory location from 2 different main memory pages frequently, cache hit ratio has no effect.
5. Search time is more as the cache control logic examines every block’s tag for a match. 

Direct mapped cache :

1. Needs only one comparison because of using direct formula to get the effective cache address.
2. Main Memory Address is divided into 3 fields : TAG, BLOCK & WORD. The BLOCK & WORD together make an index. The least significant TAG bits identify a unique word within a block of main memory, the BLOCK bits specify one of the blocks and the Tag bits are the most significant bits.
3. There is one possible location in the cache organization for each block from main memory because we have a fixed formula.
4. If the processor need to access same memory location from 2 different main memory pages frequently, cache hit ratio decreases.
5. Search time is less here because there is one possible location in the cache organization for each block from main memory.