24. Given the following Omega network, which allows 8 CPUs (P0 through P7) to access 8 memory modules (M0 through M7):
a) Show how the following connections through the network are achieved (explain how each switch must be set). Refer to the switches as 1A, 2B, etc.:
i) P0 → M2
ii) P4 → M4
iii) P6 → M3
b) Can these connections occur simultaneously or do they conflict? Explain.
c) List a processor-to-memory access that conflicts (is blocked) by the access P0 → M2 that is not listed in part (a).
d) List a processor-to-memory access that is not blocked by the access P0 → M2 and is not listed in part (a).
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