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Authors:
Linda Null ,julia Lobur
Chapter:
Alternative Architectures
Exercise:
Exercises
Question:33 | ISBN:9780763704445 | Edition: 3

Question

33. Indicate whether each of the following applies to CISC or RISC by placing either a C (for CISC) or an R (for RISC) in the blank.

_____ 1. Simple instructions averaging one clock cycle to execute.

_____ 2. Single register set.

_____ 3. Complexity is in the compiler.

_____ 4. Highly pipelined.

_____ 5. Any instruction can reference memory.

_____ 6. Instructions are interpreted by the microprogram.

_____ 7. Fixed length, easily decoded instruction format.

_____ 8. Highly specialized, infrequently used instructions.

_____ 9. Use of overlapping register windows.

_____ 10. Relatively few addressing modes.

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Answer

  R      1. Simple instructions averaging one clock cycle to execute.

  R      2. Single register set.

  R      3. Complexity is in the compiler.

  C    4. Highly pipelined.

  C   5. Any instruction can reference memory.

  C    6. Instructions are interpreted by the microprogram.

  C    7. Fixed length, easily decoded instruction format.

  C    8. Highly specialized, infrequently used instructions.

  R      9. Use of overlapping register windows.

  R     10. Relatively few addressing modes.

 

Explanation:

Here, R denotes RISC and C denotes CISC.  RISC stands for Reduced Instruction Set Computer, while CISC stands for Complex Instruction Set Computer. They represent two different instruction set architectures (ISAs) used in computer processor design.

Key features of RISC architectures include:

  • Simple Instructions: RISC instructions are typically simple and perform basic operations, such as arithmetic, logical, and data movement.

  • Single Register Set: RISC architectures typically have a single unified register set that is used for general-purpose data storage and calculations.

  • Compiler Complexity: RISC architectures rely on optimizing compilers to efficiently schedule and manage instructions, as the burden of instruction sequencing and optimization is shifted from the hardware to the software (compiler).

  • Highly Pipelined: RISC architectures often have highly pipelined designs, allowing for instruction fetch, decode, and execution to occur simultaneously in different stages of the pipeline.

CISC (Complex Instruction Set Computer): CISC is a processor architecture that emphasizes providing a wide variety of complex and powerful instructions. CISC architectures have a larger and more diverse instruction set, with instructions that can perform multiple complex operations within a single instruction. CISC processors may have instructions that operate on memory directly or have variable-length instruction formats. Examples of CISC architectures include x86 (Intel and AMD processors), IBM System/360, and DEC VAX.

Key features of CISC architectures include:

  • Complex Instructions: CISC instructions are often complex, allowing them to perform multiple operations or access memory directly. These instructions may include operations like string manipulation, decimal arithmetic, or even complex operations like floating-point calculations.

  • Any Instruction Can Reference Memory: CISC architectures often allow any instruction to access memory directly, reducing the need for explicit load/store instructions.

  • Instructions Interpreted by Microprogram: CISC architectures typically use microcode, a lower-level program that interprets the complex instructions and orchestrates the execution of simpler micro-operations within the processor.

  • Fixed-Length and Easily Decoded Instruction Format: CISC instructions may have variable-length formats, making instruction decoding more complex. However, modern CISC processors often use microcode or instruction decoders to efficiently decode and execute instructions.

  • Highly Specialized, Infrequently Used Instructions: CISC architectures may include specialized and less frequently used instructions that provide specific functionality. These instructions cater to specific tasks or uncommon operations.

 

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